1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same. More particularly, the present invention relates to a semiconductor device that includes a stacked structure of plural core chips and an information processing system including the same.
2. Description of the Related Art
A memory capacity that is required in a semiconductor device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there has been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural core chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor device that has a large memory capacity and a high operation speed as a whole.
JP-A No. 2007-157266 discloses a structure having core chips (DRAM chips) stacked in five layers, having an interface chip stacked thereon, and having these chips connected together through a through silicon via (hereinafter, “TSV”). JP-A No. 2008-251964 discloses a structure of a TSV in a chip-stack semiconductor device in detail. The semiconductor device described in JP-A No. 2008-251964 includes a TSV that penetrates a semiconductor substrate and a ring-shaped isolation trench provided by penetrating a silicon substrate to surround the TSV. One end of the TSV is connected to a wiring through a connection electrode. The connection electrode is formed by having an electrode material embedded into an opening that penetrates an interlayer dielectric film of an element forming layer, and the wiring is connected to the TSV through this connection electrode.
According to JP-A No. 2008-251964, the TSV penetrates a semiconductor substrate. A parasitic capacitance is generated between the semiconductor substrate (a ground potential) and the TSV (a signal or a power source). The parasitic capacitance needs to be as small as possible because it causes a negative influence on the TSV of a signal system such as degrading its signal quality. However, when a parasitic capacitance of a TSV of a power source system and the parasitic capacitance of the TSV of the signal system are decreased, stability of a power source potential is degraded.
The connection electrode connected to the one end of the TSV is formed by having an electrode material embedded into a large opening formed on the interlayer dielectric film of the element forming layer. However, it is very difficult to achieve both a process of forming a very small through-hole to form an element and a process of forming a very large opening for the connection electrode in the same process. Therefore, it is necessary to perform separate processes.